1. Field of the Invention
The present invention relates to a memory interface and an operation method of the memory interface.
2. Description of Related Art
With advancement of information processing technique, a semiconductor memory device is possible to perform a high speed operation with less consumed power. As such a semiconductor memory device, a technique is known which uses a data strobe signal (DQS). The semiconductor memory devices are exemplified by semiconductor storage devices having a data transfer rate in a Gbps order such as DDR2 (Double Data Rate 2) SDRAM (Synchronous DRAM) and DDR3 SDRAM.
Generally, a memory interface is interposed between a high-speed semiconductor memory device and a central processing unit (CPU). The commercially available semiconductor storage devices such as DDR2 SDRAM and DDR3 SDRAM have unstable logical states of internal circuits immediately after power-on. In the semiconductor memory devices, initialization by the memory interface is performed immediately after power-on in order to ensure a normal operation.
FIG. 1 is a flow chart showing an initializing operation of a conventional semiconductor memory device. Referring to FIG. 1, at Step S1, an I/O and a memory are enabled and initial values thereof are set. After that, at Step S2, timing calibration is carried out. Then, at Step S3, an initialization sequence is ended and start of a normal operation is prepared.
FIGS. 2A to 2C are block diagrams showing configurations and an operation of the above-mentioned timing calibration. The timing calibration is performed based on control both on a memory side and an interface side. FIG. 2A is a diagram showing a first phase of timing calibration. FIG. 2B is a diagram showing a second phase of timing calibration. FIG. 2C is a diagram showing a third phase of timing calibration. Referring to FIG. 2A, in the first phase of the timing calibration, a transfer rate is decreased and data for read calibration (for example, PRBS 27-1) is written. Referring to FIG. 2B, in the second phase, skew adjustment of DQ and DQS on a read side is performed using the written data. Referring to FIG. 2C, in the third phase, the skew adjustment of DQ and DQS on write side is performed.
In a conventional skew adjustment, when physical limitations (for example, limitations that can be adjusted by a designer, such as variations in relative accuracy and substrate wiring) cannot be suppressed on the write side, a mode is changed to an SDR mode or the transfer rate is decreased to reliably write data. The method requires a function to safely switch a frequency dividing ratio and a mode of a clock in a normal mode “on the fly” and a test circuit. A test requires a pseudo random pattern such as PRBS (pseudo random bit sequence). For example, when the above-mentioned timing calibration is performed using a particular pattern length such as PRBS7 stages, the following three processes:                “Write of Read data”,        “Calibration of Read”, and        “Calibration of Write”must be performed.        
When data cannot be correctly read in read, it is difficult to determine whether it is caused due to failure of initial write or a problem in the read. When the initial write fails, the write needs to be performed again by decreasing the frequency.
In addition to the above-mentioned technique, another technique of a memory interface circuit has been known. Japanese Patent Application Publication (JP-P2007-058990A: first conventional example) describes a method of allowing a loopback test in an interface in which phase relationship between data and a strobe signal for sampling the data varies between an input and an output. Referring to the first conventional example, to test phase shift on an input side and a sampling circuit, DQ and DQS are outputted in the same phase in a phase shift circuit on an output side and DQS is shifted by the phase shift circuit by 90 degrees and sampled by the sampling circuit. To test a function on the output side, the phase shift circuit is controlled so as not to shift the phase of DQS on the input side. The phase shift circuit on the output side sets phase shift of the data sampling clock to 90 degrees and fixes phase shift of DQS to 180 degrees. The sampling circuit samples the loop-backed DQ based on DQS phase-shifted by 90 degrees.
Japanese Patent Application Publication (JP-P2008-052335A: second conventional example) describes another technique related to an interface circuit having a calibration circuit for automatically detecting a data effective window of a data signal and adjusting an optimum delay amount of a strobe signal and a data signal delay circuit. Given that a minimum delay amount in the calibration circuit is tMINDLY, a skew between the data signal and the strobe signal is tSKEW, and a set-up time of the data signal is tSETUP, the data signal delay circuit delays the data signal by a delay amount tFIXDLY which satisfy tFIXDLY>tMINDLY+tSKEW−tSETUP.
As described above, when the timing calibration is performed, when first write cannot be reliably performed, the conventional memory interface cannot read normal data in read. For this reason, in the conventional memory interface, when data cannot be completely read in the read, it is difficult to determine whether the failure is due to failure of the first write, failure of fetching of data or a problem in the read in spite of success of the first write. Especially, in a semiconductor memory device which transmits data at high speed, a rate of jitter due to reflection in 1-bit length, ISI (inter stimulus interval), IR drop and the like has increased because of speeding up and miniaturization in process. Thus, for a memory interface for such a semiconductor memory device, there is a demand for a technique capable of stably reading and writing data even when the rate of jitter is large.